1. Field of the Invention
The present invention relates to a display device and a method of fabricating a display device, and more particularly to a liquid crystal display (LCD) device and a method of fabricating an LCD device.
2. Description of the Related Art
As demand for displaying information increases, demand for flat panel display devices having slim profiles, light weight, and low power consumption increases. Among the different types of flat panel display devices, LCD devices are commonly used for their superior color reproduction.
In general, an LCD device includes two substrates facing each other, wherein electrodes are formed on opposing facing surfaces of the two substrates, and a liquid crystal material is injected into a space defined between the two substrates. The LCD device displays images by applying a voltage between the electrodes on both the substrates to induce an electric field to the liquid crystal material, thereby changing alignment orientation of liquid crystal molecules of the liquid crystal material to vary light transmittance through the liquid crystal material.
The first of the two substrates of the LCD device includes a matrix array of thin film transistors (TFTs), wherein an active layer of each of the TFTs is generally formed of amorphous silicon (a-Si:H). This is because the amorphous silicon can be formed on large-sized glass substrates at relatively low temperatures.
However, some types of LCD devices employ TFTs using polycrystalline silicon (polysilicon) as an active layer. Since the polysilicon has an electric field effect mobility, which is 100 to 200 times greater than that of amorphous silicon, the LCD employing polysilicon TFTs has fast response speeds and stability against extreme temperature ranges and light. In addition, since driving circuits can be formed on the substrate, it is possible to reduce fabrication costs of the LCD device.
The polysilicon can be formed using various different methods, such as laser annealing, metal induced crystallization (MIC), and solid phase crystallization (SPC). During the laser annealing method, a laser beam is irradiated onto an amorphous silicon layer using an excimer laser while heating the substrate to a temperature of 250° C., thereby growing a polysilicon layer. During the MIC method, a metal film is deposited onto an amorphous silicon layer and a polysilicon layer is grown using the metal film as a seed for nucleation. During the SPC method, an amorphous silicon layer is annealed at high temperature for an extended period of time. In addition to these different types of methods, another method includes depositing a polysilicon layer directly onto a substrate.
Currently, a new crystallization method has been developed that uses sequential lateral solidification (SLS). The SLS method makes use of the fact that silicon grains grow along a perpendicular direction to a boundary between a liquid silicon regime and a solid silicon regime. In addition, during the SLS method, the energy level and irradiation range of a laser beam are properly controlled to control lateral grain growth along a predetermined length, thereby increasing the grain size.
FIGS. 1A to 1E are schematic cross sectional views of a method of fabricating a Buried Bus Coplanar (BBC) polysilicon TFT according to the related art. In FIG. 1A, a data bus line 130 of a first metal film is formed on a substrate 110.
In FIG. 1B, an interlayer insulating layer 135 formed of an inorganic material, such as SiNx or SiOx, or an organic insulator is formed on the data bus line 130 and the substrate 110. Then, a semiconductor layer 180 of polysilicon is formed having a predetermined pattern on the interlayer insulating layer 135.
In FIG. 1C, a gate insulating layer 125 of inorganic material is formed on the semiconductor 180 and the substrate 110. Then, a gate electrode 120 and a gate bus line (not shown) are formed on the gate insulating layer 125 by depositing a second metal film on the gate insulating layer 125 and patterning the second metal film. Next, P+ impurity ions are implanted into the semiconductor layer 180 using the gate electrode 120 as a mask. Then, the implanted impurity ions are activated by a laser beam, thereby forming a source region and a drain region at predetermined portions of the semiconductor layer 180.
In FIG. 1D, a passivation layer 165 of inorganic or organic material is formed on the gate electrode 120 and the gate insulating layer 125. Then, a first contact hole exposing a part of the data bus line 130, and second and third contact holes 109b and 109c exposing a part of the semiconductor layer 180 are formed in the passivation layer 165.
In FIG. 1E, an indium tin oxide (ITO) layer is deposited on the passivation layer 165 including the first, second, and third contact holes 109a, 109b, and 109c, and is then patterned, thereby forming a pixel electrode 140 electrically in contact with the impurity-doped semiconductor layer 180. During formation of the pixel electrode 140, a source electrode 140a is formed by electrically connecting the data bus line 130 with the impurity-doped semiconductor layer 180 through the first contact hole 109a and the second contact hole 109b. In addition, a drain electrode is formed together with the pixel electrode 140 by the ITO layer filled within the third contact hole 109c. 
Then, as the first, second, and third contact holes 109a, 109b, and 109c are formed, an exposed portion of the data bus line 130 and exposed portions of the semiconductor layer 180 are oxidized. Hence, contact resistance between the ITO layer filled within the first contact hole 109a and the exposed data bus line 130 increases. Similarly, contact resistance between the ITO layer filled within the second and third contact holes 109b and 109c and the exposed semiconductor layer 180 increases. Accordingly, the increased contact resistances causes signal delays, thereby reducing image quality and reliability of the LCD device.
In addition, the data bus line 130 including the source electrode is positioned below the semiconductor layer 180. After the data bus line 130 is formed, the interlayer insulating layer 135 is deposited at a thickness of 3,000 Å, and the semiconductor layer 180 is formed. Accordingly, the semiconductor layer 180 formed of amorphous silicon has different thicknesses between a stepped portion and a plane portion. Due to the different thicknesses, the polysilicon layer, which is crystallized by laser annealing of the amorphous silicon, becomes very thin at a predetermined portion so that non-uniform crystalline property of the active region and ablation phenomenon occur.
In FIG. 1D, the first contact hole 109a is formed by etching the passivation layer 165, the gate insulating layer 125, and the interlayer insulating layer 135 to expose a portion of the data bus line 130. The second and third contact holes 109b and 109c are formed by etching the passivation layer 165 and the gate insulating layer 125 to expose portions of the semiconductor layer 180. When the first, second, and third contact holes 109a, 109b, and 109c are formed, the impurity-doped semiconductor layer 180 is subject to etching damage, thereby deteriorating operational characteristics of the LCD device due to partial loss of semiconductor layer 180.